RISC-V

At the GNU Tools Cauldron, my colleague, Jeremy Bennett, showed how the long established GNU tool, CGEN, can be used to create an assembler, disassembler and simulator from a semi-formal description of the RISC-V architecture in Scheme (https://gcc.gnu.org/wiki/cauldron2018#cgen).

However the CGEN specification in Scheme is far from rigorous by today's standards. Alastair Reid of ARM has shown how SAIL can be used to define rigorous semantics for RISC-V in a paper to be presented at POPL in January 2019 (https://alastairreid.github.io/papers/POPL_19/).

In this talk I shall show how a SAIL specification can be transformed into a CGEN framework. Using this approach, a rigorous SAIL semantic specification can be used to generate a practical GNU assembler, disassembler and simulator.

This will is a work in progress - the project is not due to finish until May 2019. I shall explore the general approach used, and the areas where the greater rigour of SAIL runs into problems with the limitations of CGEN Scheme specification.